Phase/frequency detectors are typically used in phase locked loops in clock recovery systems. A clock recovery system is used to recover a clock signal from a data stream which has passed along a data transmission system, for example between a transmitter and a receiver, each of which can be comprised of an integrated circuit.
A schematic of a well known phase/frequency detector, called a Hogge phase detector is shown in FIG. 1. This structure is comprised of a pair of static D-type flip flops 1 and 2, flip flop 1 having its Q output connected to an input of an exclusive OR (XOR) gate 3, and flip flop 2 having its Q output connected to an input of an XOR gate 4. An input data signal is applied to the D input of flip flop 1 as well as to the other input of XOR gate 3, and a clock signal CLOCK is applied to the clock input of flip flop 1. A complementary clock signal/CLOCK is applied to the clock input of flip flop 2. The Q output of flip flop 1 is also connected to the second input of XOR 4 as well as to the D input of flip flop 2.
The function of the circuit is to compare the input non-return-to-zero (NRZ) data signal to the clock signal. In operation, when the positive edge of the recovered clock is aligned to the center of the data eye, then DC components of pulse signals A and B which are presented at the A and B outputs of the XORs are equal (i.e. both the positive and negative excursions of the NRZ output signals are equal, and the time periods of these excursions are equal).
When the positive edge of the recovered clock signal is delayed with respect to the center of the data eye, then the DC component of the signal A is greater than B. When the positive edge of the recovered clock is advanced with respect to the center of the data eye, the DC component of the signal A is smaller than B.
The output signals A and B can be used to drive a charge pump. Since the DC values of signals A and B contain information about the relationship between the clock and the data, the outputs can be coupled to a voltage or current up-down generator which drives a voltage or current controlled oscillator, which is contained in a loop with a loop filter and optionally a divider, to form a phase locked loop system.
This design requires both a clock and a complementary clock signal to drive the two flip flops 1 and 2. Any skew between these clock signals creates problems in high-speed applications. In particular, random delay can create a large dead zone and reduce linearity. Difficulty in high speed operation is a major shortcoming of the above design. The maximum operating frequency of the static Hogge detector constructed using a 0.35 .mu.m CMOS process has been shown to be about 300 Mb/s, and about 250 Mb/s using a 0.8 .mu.m CMOS process.